Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops

Use of a standard non-rad-hard digital cell library in the rad-hard design can be cost-effective solution for space applications. In this paper we demonstrate how flip-flop, as one most vulnerable cells, converted into flip-flop without modifying its internal structure. We present five variants Triple Modular Redundancy (TMR) flip-flop: baseline TMR latch-based True-Single Phase Clock (TSPC) scannable and self-correcting flip-flop. For all variants, multi-bit upsets have been addressed by applying special placement constraints, while Single Event Transient (SET) mitigation was achieved through usage customized SET filters selection optimal inverter sizes clock reset trees. The proposed feature differing performance, thus enabling to choose every sensitive node circuit, according predefined constraints. Several designs validated on IHP’s 130nm BiCMOS process, irradiation custom-designed shift registers. It has shown that flip-flops are robust soft errors with threshold Linear Energy Transfer (LET) from ( $32.4\, \frac { {\mathrm \text {M} {eV} }}\cdot {c} {m} }}^{2}}{ {g} }}}$ ) notation="LaTeX">$62.5\, ), depending variant.